Kbase 15144: Cache problem suspected on Intel based SMP cpu's - UNISYS
| Autor |
Progress Software Corporation - Progress |
| Acesso |
Público |
| Publicação |
5/10/1998 |
|
Cache problem suspected on Intel based SMP cpu's - UNISYS
Shared memory locking problem on Intel-based SMP systems
NOTE: the following problem is most likely in other Intel Pentium
based SMP implementations since the intel on-chip memory controller is
the culprit, the following information is specific to UNISYS hardware
and should not be generally applied to other hardware platforms
without first consulting with the vendor.
UNISYS U2000 Model 550 and Model 590's have some processor boards that
use the intel memory controller which has a design flaw that can cause
shared memory locking problems resulting in corrupt memory and could
corrupt a database. This problem is not likely to happen on a
customer system, but is possible.
There is a simple check that can be performed in software to determine
if a specific customer's system may have this problem using the get
hardware inventory command from root:
# gethinv -A cpu
index status class type fpu speed capability model
0 on i Pentium i387 91 0x1bf 0x521
1 on i Pentium i387 ? 0x1bf 0x521
In the 6th column is displayed the speed of the 1st processor board in
the system. If it says 60+ or 90+ then those processor boards do have
the design flaw. 120 and 133 Mhz boards do not have the problem. Note
that since systems can contain a mix of processor speeds, this command
is not sufficient to determine if all boards are ok only the first
one. The example above has a 90MHz board which has the design flaw.
Workaround: Current workaround is to replace all processor boards with
boards that contain at least 120MHz processors. UNISYS is working
with us to provide a workaround in software, but that has not been
finalized.
Progress Software Technical Support Note # 15144